Milwaukee 6184-01 Operations Instructions download pdf (Page 42)

and

no

Delay

Gate

occurs

.

Unity-gain

buffer

U535A

couples

the

voltage

from

the

ACQUIRE-STOP

DELAY

control

to

the

comparator

.

When

the

Sweep

Ramp

voltage

at

the

base

of

Q522A

exceeds

the reference

voltage

from

U535A,

Q522A

shuts

off

and

0512B

turns

on

.

Because

Q522A

is

turned

off,

the

low

level

at

its

collector

turns

off

Q564,

the

input

of

Schmitt

trigger

pair

Q564-Q568

.

With

Q564

turned

off,

Q568

conducts

a

greater

current

through

0574

.

The

Delay

Gate

Generator

(DGG)

produces

the

Delay

Gate

signal

in

response

to

the output

of

the

Delay

Time

Comparator

and

the Z-Axis

Gate

line

.

The

DGG

consists

of

Q572

and

Q574

.

The

Delay

Gate

starts

when

a low-logic

level

on

the

Z-

Axis

Gate

line

turns

Q572

off

.

When

Q572

is

shut

off,

0574

conducts

all

the

current

from

Q568,which

is

off

because

the

Sweep

Ramp

voltage

is

lower

than

the

voltage

from

the

ACQUIRE-STOP

DELAY

control

.

This

causes

Q574's

collector

voltage

to

produce

a

positive

transition,

which

is

the

leading

edge

of

the

Delay

Gate

.

When

the

Sweep

Ramp

voltage

exceeds

the

voltage

from

the

ACQUIRE-STOP

DELAY

control,

Q522A

turns

off

and

Q512B

turns

on

.

This

causes

the

Schmitt

trigger

transistor

Q568

to

conduct

a

greater current

through

Figure 3-6

.

Timing

of

events

that

form

the

Delay

Gate

signal

.

Theory

of

Operation--71387

Q574,

whose

collector

voltage

falls

and

forms

the

trailing

edge

of

the

Delay

Gate

.

Emitter-follower

Q578

applies

the

Delay

Gate

to

pin

B9

of

the

Interface

Board's

edge

connector

.

Figure3-6

shows

the timing

of the

events

that

form

the

Delay

Gate

Signal

.

If

the

71387

is in

the

A

Horiz

plug-in

compartmentand

the

INTERNAL

AQSCLOCK/AQR

button

is

pressed,

S645

grounds

the

Delay

Mode

line

.

The

Delay

Mode

line

turns

on 0576,which

saturates

and

removes

the

collector

voltage

from

0574

.

In

this

situation

the

Delay

Gate

line

stays

at

a

low-logic

level

.

This

permits

a

time

base

in

the

B

Horiz

plug-in

compartment

to

operate

independently

.

IGITAL

VOLTMETER

The

Digital

Voltmeter

circuit

converts

the

Delay

Comparison

Voltage,

determined

by

the

ACQUIRE-STOP

DELAY

front-panel

control,

to

an

accurate

time

measurement

which

is

displayed

on

the

crt

by

the

mainframe

readout

system

.

The

schematic

for

the

Digital

Voltmeter

circuit

is

shown

on

diagram

5

.

SWEEP

TRIGGER

EVENT

2788-106

3-

1 1

Z-AXIS

GATE

II

II

II

II

II

II

I

I

II

11

Q568

COLLECTOR

I

I

I

II

I

I

II

11

I

I

II

DELAY

GATE

11

I

Q574COLLECTOR

II

I

I

II

(I

I

I

II

II

I

II

BRIEF

I

DELAY

"ACQUIRE

STOP"

I I

VOLTAGE

FROM

ACQUIRE-$1

OP

I I

DELAY

CONTROL

1 2 ... 37 38 39 40 41 42 43 44 45 46 47 ... 142 143

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